1. Field of the Invention
This invention relates to a semiconductor device. More particularly, it relates to a semiconductor device including an element, such as a resistor cell array, which is formed in a semiconductor layer but which is not provided with a control electrode layer, such as a polysilicon layer, provided on top of the semiconductor layer.
2. Description of Related Art
In general, a supply power generation circuit mounted on a semiconductor device along with a logic circuit constructed by a MIS transistor, a memory and so forth, is constructed by a circuit that makes use preferentially of a plurality of resistor cells. In a layout pattern of such resistor cells, a diffused layer resistor, constructed by a diffused layer of a high sheet resistance, is preferentially used. The resistors cell layout pattern is constructed by arranging several to tens of arrays of the diffused layer resistors as shown in FIGS. 4A and 4B (related art example 1). In FIGS. 4A and 4B, it is necessary to protect a diffused layer resistor 107 (N-diffused layer) from adverse effects of noise from a semiconductor substrate (P-sub) 101 or noise from neighboring diffused layer resistors 107. To this end, each diffused layer resistor 107 (N-diffused layer) is formed in a region of a P-well 105 (P-well) surrounded by a deep-N-well 102 (deep N-well) and by an N-well 103 (N-well). The diffused layer resistor 107 (N− diffused layer) is surrounded by a P-well contact 106 (P+ diffused layer), which in turn is surrounded by an N-well contact 104 (N+ diffused layer).
[Patent Document 1]
JP Patent Kokai Publication No. JP2003-133315A